Conventional die-level packaged microelectronic devices include a microelectronic die, an interposer substrate or lead frame attached to the die, and a molded casing around the die. The die generally includes an integrated circuit and a plurality of bond-pads coupled to the integrated circuit. The bond-pads are typically coupled to terminals on the interposer substrate or lead frame and serve as external electrical contacts on the die through which supply voltage, signals, etc., are transmitted to and from the integrated circuit. In addition to the terminals, the interposer substrate also includes ball-pads coupled to the terminals by conductive traces supported in a dielectric material. Solder balls can be attached to the ball-pads in one-to-one correspondence to define a “ball-grid array.” Packaged microelectronic devices with ball-grid arrays are generally higher grade packages having lower profiles and higher pin counts than conventional packages using lead frames.
One process for packaging a die with a ball-grid array at the die level includes (a) forming a plurality of dies on a semiconductor wafer, (b) cutting the wafer to separate or singulate the dies, (c) attaching individual dies to an interposer substrate, (d) wire-bonding the bond-pads of the dies to the terminals of the interposer substrate, and (e) encapsulating the dies with a suitable molding compound. Mounting individual dies to interposer substrates or lead frames in the foregoing manner can be a time-consuming and expensive process. In addition, forming robust wire-bonds that can withstand the forces involved in molding processes becomes more difficult as the demand for higher pin counts and smaller packages increases. Moreover, the process of attaching individual dies to interposer substrates or lead frames may damage the bare dies. These difficulties have made the packaging process a significant factor in the production of microelectronic devices.
Another process for packaging microelectronic devices is wafer-level packaging. In this process, a plurality of microelectronic dies are formed on a wafer, and then a redistribution layer is formed over the dies. The redistribution layer can include a dielectric layer and a plurality of exposed pads formed in arrays on the dielectric layer. Each pad array is typically arranged over a corresponding die, and the pads in each array are coupled to corresponding bond-pads of the die by conductive traces extending through the dielectric layer. After forming the redistribution layer on the wafer, discrete masses of solder paste can be deposited onto the individual pads. The solder paste is then reflowed to form small solder balls or “solder bumps” on the pads. After forming the solder balls, the wafer is singulated to separate the individual microelectronic devices from each other.
Wafer-level packaging is a promising development for increasing efficiency and reducing the cost of microelectronic devices. By “pre-packaging” individual dies with a redistribution layer before cutting the wafers to singulate the dies, sophisticated semiconductor processing techniques can be used to form smaller arrays of solder balls. Additionally, wafer-level packaging is an efficient process that simultaneously packages a plurality of dies, thereby reducing costs and increasing throughput.
Conventional processes of forming a redistribution layer on a wafer include (a) depositing first and second dielectric layers on the wafer, (b) patterning and developing the second dielectric layer to form holes over the bond-pads on the dies, (c) reaction ion etching the first dielectric layer to expose the bond-pads, (d) depositing a conductive layer across the wafer, (e) forming a resist on the conductive layer, (f) patterning and developing the resist, (g) etching the exposed sections of the conductive layer to form the pads, and (h) removing the resist from the wafer. One concern with forming a redistribution layer on a wafer is that conventional processes are relatively expensive because patterning the second dielectric layer requires a first mask and patterning the resist requires a second mask. Masks are expensive and time-consuming to construct because they require very expensive photolithography equipment to achieve the tolerances required in semiconductor devices. Accordingly, there is a need to reduce the cost of forming redistribution layers.